Semiconductor device

ABSTRACT

A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to, for example, a semiconductor, atransistor, and a semiconductor device. The present invention relatesto, for example, a method for manufacturing a semiconductor, atransistor, and a semiconductor device. The present invention relatesto, for example, a semiconductor, a display device, a light-emittingdevice, a lighting device, a power storage device, a memory device, aprocessor, and an electronic device. The present invention relates to amethod for manufacturing a semiconductor, a display device, a liquidcrystal display device, a light-emitting device, a memory device, and anelectronic device. The present invention relates to a driving method ofa semiconductor device, a display device, a liquid crystal displaydevice, a light-emitting device, a memory device, and an electronicdevice.

Note that one embodiment of the present invention is not limited to theabove technical field. The technical field of one embodiment of theinvention disclosed in this specification and the like relates to anobject, a method, or a manufacturing method. In addition, one embodimentof the present invention relates to a process, a machine, manufacture,or a composition of matter.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. A display device, a light-emitting device, a lightingdevice, an electro-optical device, a semiconductor circuit, and anelectronic device include a semiconductor device in some cases.

2. Description of the Related Art

A memory device including a semiconductor has attracted attention as ahigh capacity memory device included in a computer and the like. Inparticular, it has been known that the integration degree of a NANDflash memory is easily heightened because the NAND flash memory has asmall number of wirings or electrodes per memory cell. Storage capacityhas been increased year by year because of realization of technologysuch as multivalued memory. In recent years, two-dimensional memory cellarrangement has approached limits on higher integration and is beingreplaced with technology of three-dimensional memory cell arrangement(see Patent Document 1).

REFERENCE Patent Document [Patent Document 1] Japanese Published PatentApplication No. 2011-96340 SUMMARY OF THE INVENTION

An object is to provide a highly integrated semiconductor device.Another object is to provide a semiconductor device withthree-dimensional memory cell arrangement. Another object is to providea semiconductor device with large storage capacity. Another object is toprovide a semiconductor device with a long retention period.

Another object is to provide a module including any of the abovesemiconductor devices. Another object is to provide an electronic deviceincluding any of the above semiconductor devices or the module. Anotherobject is to provide a novel semiconductor device. Another object is toprovide a novel module. Another object is to provide a novel electronicdevice.

Another object is to provide a transistor having normally-off electricalcharacteristics. Another object is to provide a transistor having a lowleakage current in an off state. Another object is to provide atransistor having a small subthreshold swing value. Another object is toprovide a transistor having a small short-channel effect. Another objectis to provide a transistor having excellent electrical characteristics.Another object is to provide a transistor having high reliability.Another object is to provide a transistor with high frequencycharacteristics.

Note that the descriptions of these objects do not disturb the existenceof other objects. In one embodiment of the present invention, there isno need to achieve all the objects. Other objects will be apparent fromand can be derived from the description of the specification, thedrawings, the claims, and the like.

(1)

One embodiment of the present invention is a semiconductor device thatincludes a substrate, a prism-like insulator, a memory cell stringincluding a plurality of transistors connected in series. The prism-likeinsulator is provided over the substrate, and the memory cell string isprovided on the side surface of the prism-like insulator.

(2)

One embodiment of the present invention is a semiconductor device thatincludes a substrate, a prism-like insulator, a plurality of memory cellstrings. The plurality of memory cell strings each comprise a pluralityof transistors connected in series. The prism-like insulator is providedover the substrate, and the plurality of memory cell strings each areprovided on a side surface of the prism-like insulator.

(3)

One embodiment of the present invention is the semiconductor deviceaccording to (1) or (2), in which the plurality of transistors eachinclude a gate insulator and a gate electrode, the gate insulatorincludes a first insulator, a second insulator, and a chargeaccumulation layer, and the charge accumulation layer is positionedbetween the first insulator and the second insulator.

(4)

One embodiment of the present invention is the semiconductor deviceaccording to any one of (1) to (3), in which the plurality oftransistors include an oxide semiconductor.

(5)

One embodiment of the present invention is the semiconductor deviceaccording to (4), in which the oxide semiconductor contains indium, anelement M (aluminum, gallium, yttrium, or tin), and zinc.

(6)

One embodiment of the present invention is the semiconductor deviceaccording to any one of (1) to (5) which further includes a firsttransistor and a second transistor provided over the substrate. A sourceterminal of the first transistor is electrically connected to a firstterminal of the memory cell string and a drain terminal of the secondtransistor is electrically connected to a second terminal of the memorycell string.

(7)

One embodiment of the present invention is the semiconductor deviceaccording to (6), in which the first transistor and the secondtransistor include single crystal silicon.

A highly integrated semiconductor device can be provided. Asemiconductor device with three-dimensional memory cell arrangement canbe provided. A semiconductor device with large storage capacity can beprovided. A semiconductor device with a long retention period can beprovided.

A module including any of the above semiconductor devices can beprovided. An electronic device including any of the above semiconductordevices or the module can be provided. A novel semiconductor device canbe provided. A novel module can be provided. A novel electronic devicecan be provided.

A transistor having normally-off electrical characteristics can beprovided. A transistor having a low leakage current in an off state canbe provided. A transistor having a small subthreshold swing value can beprovided. A transistor having a small short-channel effect can beprovided. A transistor having excellent electrical characteristics canbe provided. A transistor having high reliability can be provided. Atransistor with high frequency characteristics can be provided.

Note that the description of these effects does not disturb theexistence of other effects. One embodiment of the present invention doesnot necessarily achieve all the effects listed above. Other effects willbe apparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are a cross-sectional view and a circuit diagram of asemiconductor device of one embodiment of the present invention;

FIGS. 2A and 2B are a schematic view and a cross-sectional viewillustrating operation of a semiconductor device of one embodiment ofthe present invention;

FIGS. 3A and 3B are circuit diagrams illustrating operation of asemiconductor device of one embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating operation of a semiconductordevice of one embodiment of the present invention;

FIG. 5 is a circuit diagram illustrating operation of a semiconductordevice of one embodiment of the present invention;

FIG. 6 is a circuit diagram illustrating operation of a semiconductordevice of one embodiment of the present invention;

FIG. 7 is a circuit diagram illustrating operation of a semiconductordevice of one embodiment of the present invention;

FIG. 8 is a circuit diagram illustrating operation of a semiconductordevice of one embodiment of the present invention;

FIG. 9 is a circuit diagram illustrating operation of a semiconductordevice of one embodiment of the present invention;

FIG. 10 is a cross-sectional view of a semiconductor device of oneembodiment of the present invention;

FIG. 11 is a cross-sectional view of a semiconductor device of oneembodiment of the present invention;

FIG. 12 is a band diagram of a channel formation region in a transistorof one embodiment of the present invention and its vicinity thereof;

FIG. 13 is a triangular diagram for explaining composition of an In-M-Znoxide;

FIGS. 14A to 14E show structural analysis of a CAAC-OS and a singlecrystal oxide semiconductor by XRD and selected-area electrondiffraction patterns of a CAAC-OS;

FIGS. 15A to 15E show a cross-sectional TEM image and plan-view TEMimages of a CAAC-OS and images obtained through analysis thereof:

FIGS. 16A to 16D show electron diffraction patterns and across-sectional TEM image of an nc-OS;

FIGS. 17A and 17B show cross-sectional TEM images of an a-like OS; and

FIG. 18 shows a change of crystal parts of an In—Ga—Zn oxide owing toelectron irradiation.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described in detail withreference to the drawings. However, the present invention is not limitedto the description below, and it is easily understood by those skilledin the art that modes and details disclosed herein can be modified invarious ways. Furthermore, the present invention is not construed asbeing limited to description of the embodiments. In describingstructures of the invention with reference to the drawings, commonreference numerals are used for the same portions in different drawings.Note that the same hatched pattern is applied to similar parts, and thesimilar parts are not especially denoted by reference numerals in somecases.

Note that the size, the thickness of films (layers), or regions indrawings is sometimes exaggerated for simplicity.

In this specification, the terms “film” and “layer” can be interchangedwith each other.

A voltage usually refers to a potential difference between a givenpotential and a reference potential (e.g., a source potential or aground potential (GND)). A voltage can be referred to as a potential andvice versa. In general, a potential (a voltage) is relative and isdetermined depending on the difference relative to a referencepotential. Therefore, even a “ground potential,” for example, is notnecessarily 0 V. For example, in some cases, a “ground potential” is thelowest potential in a circuit. In other cases, a “ground potential” is amoderate potential in a circuit. In those cases, a positive potentialand a negative potential are set using the potential as a reference.

Note that the ordinal numbers such as “first” and “second” are used forconvenience and do not denote the order of steps or the stacking orderof layers. Therefore, for example, the term “first” can be replaced withthe term “second,” “third,” or the like as appropriate. In addition, theordinal numbers in this specification and the like do not correspond tothe ordinal numbers which specify one embodiment of the presentinvention in some cases.

Note that an impurity in a semiconductor refers to, for example,elements other than the main components of the semiconductor. Forexample, an element with a concentration of lower than 0.1 atomic % isan impurity. When an impurity is contained, the density of states (DOS)may be formed in a semiconductor, the carrier mobility may be decreased,or the crystallinity may be decreased, for example. In the case wherethe semiconductor is an oxide semiconductor, examples of an impuritywhich changes characteristics of the semiconductor include Group 1elements, Group 2 elements, Group 14 elements, Group 15 elements, andtransition metals other than the main components; specifically, thereare hydrogen (hydrogen is included in water), lithium, sodium, silicon,boron, phosphorus, carbon, and nitrogen, for example. In the case of anoxide semiconductor, oxygen vacancy may be formed by entry of impuritiessuch as hydrogen. Furthermore, in the case where the semiconductor issilicon, examples of an impurity which changes characteristics of thesemiconductor include oxygen, Group 1 elements except hydrogen, Group 2elements, Group 13 elements, and Group 15 elements.

Note that in this specification, the description “A has a shape suchthat an end portion extends beyond an end portion of B” may indicate,for example, the case where at least one of end portions of A ispositioned on an outer side than at least one of end portions of B in atop view or a cross-sectional view. Thus, the description “A has a shapesuch that an end portion extends beyond an end portion of B” can bealternately referred to as the description “one of end portions of A ispositioned on an outer side than one of end portions of B in a topview,” for example.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 10°, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.A term “substantially parallel” indicates that the angle formed betweentwo straight lines is greater than or equal to −30° and less than orequal 15 to 30°. In addition, the term “perpendicular” indicates thatthe angle formed between two straight lines is greater than or equal to80° and less than or equal to 100°, and accordingly also indicates thatthe angle formed between two straight lines is greater than or equal to85° and less than or equal to 95°. A term “substantially perpendicular”indicates that the angle formed between two straight lines is greaterthan or equal to 60° and less than or equal to 120°.

In this specification, trigonal and rhombohedral crystal systems areincluded in a hexagonal crystal system.

<Semiconductor Device>

A semiconductor device of one embodiment of the present invention willbe described below.

Note that the transistor is assumed to be of an n-channel type below.However, a term, a reference numeral, or the like may be replaced withan appropriate one in the following description when a p-channeltransistor is used.

<Structure of Semiconductor Device>

An example of a structure of a semiconductor device of one embodiment ofthe present invention is shown below.

FIG. 1A is a cross-sectional view of a semiconductor device of oneembodiment of the present invention. FIG. 1B is a circuit diagram of thesemiconductor device in FIG. 1A.

The semiconductor device in FIG. 1A includes a substrate 100, aninsulator 120, an insulator 122, an insulator 124, an insulator 126, aninsulator 128, an insulator 130, a conductor 140, a conductor 142, aconductor 144, a conductor 146, a conductor 148, a conductor 132, aconductor 134, a conductor 136, a conductor 138, a transistor Tr_S1, atransistor Tr_S2, and transistors Tr_to Tr_2 n (n is an integer of 2 ormore).

The transistors Tr_S1 and Tr_S2 are provided to the substrate 100.Specifically, the transistor Tr_S includes a pair of impurity regions166 provided in the substrate 100, a channel formation region placedbetween the impurity regions 166, a conductor 154 including a regionoverlapping with the channel formation region, and an insulator 162placed between the channel formation region and the conductor 154. Theconductor 154 has a function as a gate electrode and the insulator 162has a function as a gate insulator. The conductor 154, which serves as agate electrode of the transistor Tr_S1, is electrically connected to awiring SEL_1. The conductor 154, which serves as a gate electrode of thetransistor Tr_S2, is electrically connected to a wiring SEL_2. Thetransistor Tr_S2 has the same structure as that of the transistor Tr_S1,and the description of its structure is omitted; however, the transistorTr_S2 may have a different structure. The transistors Tr_S1 and Tr_S2are isolated by the insulator 120. As the element isolation method, ashallow trench isolation (STI) method, a local oxidation of silicon(LOCOS) method, or the like can be used. Note that the structures of thetransistors Tr_S1 and Tr_S2 are not limited to the structuresillustrated in FIG. 1A. For example, a transistor provided over asilicon on insulator (SOI) substrate or a FIN-type transistor may beused.

The insulator 122 is provided over the transistors Tr_S1 and Tr_S2. Theinsulator 130, and the conductors 144, 146, and 148 are provided overthe insulator 122. The insulator 130 has a prism-like shape or awall-like shape and is provided with the transistors Tr_1 to Tr_2 n (nis an integer of 2 or more) on the sides thereof. Note that the channellength direction of each of the transistors Tr_1 to Tr_n is parallel tothe direction perpendicular to a top surface of the substrate and thechannel length direction of each of the transistors Tr_n+1 to Tr_2 n isparallel to the direction perpendicular to the top surface of thesubstrate. Note that the insulator 130 does not necessarily have aprism-like shape or a wall-like shape, and may be a cylinder shape, forexample. One side of the insulator 130 is provided with the transistorsTr_1 to Tr_n, and the other side is provided with the transistors Tr_n+1to Tr_2 n. The larger n is, the more highly integrated the semiconductordevice is. For example, n may be 2, 4, 8, 16, 32, 64, or 128.

Note that the conductor 132 has a region facing the transistors Tr_1 toTr_2 n with the insulator 130 therebetween. The conductor 132 has afunction as a back gate electrode of the transistors Tr_1 to Tr_2 n(also referred to as a second gate electrode) and is electricallyconnected to a wiring BGL.

For example, the transistor Tr_1 includes an insulator 106 a, asemiconductor 106 b, an insulator 106 c, a conductor 116 a, a conductor116 b, an insulator 112 a, a charge accumulation layer 112 b, aninsulator 112 c, and a conductor 104. The insulator 106 a is providedalong the side of the insulator 130. The semiconductor 106 b is providedalong the side of the insulator 130 with the insulator 106 atherebetween. The insulator 106 c is provided along the side of theinsulator 130 with the semiconductor 106 b and the insulator 106 atherebetween. The insulator 112 a, the conductor 116 a, and theconductor 116 b each include a region facing the insulator 130 with theinsulator 106 c, the semiconductor 106 b, and the insulator 106 atherebetween. Note that the insulator 112 a is placed between theconductor 116 a and the conductor 116 b. The charge accumulation layer112 b has a region facing the insulator 130 with the insulator 112 a,the insulator 106 c, the semiconductor 106 b, and the insulator 106 atherebetween. The insulator 112 c has a region facing the insulator 130with the charge accumulation layer 112 b, the insulator 112 a, theinsulator 106 c, the semiconductor 106 b, and the insulator 106 atherebetween. The conductor 104 has a region facing the insulator 130with the insulator 112 c, the charge accumulation layer 112 b, theinsulator 112 a, the insulator 106 c, the semiconductor 106 b, and theinsulator 106 a therebetween.

Thus, in the transistor Tr_1, the semiconductor 106 b has a function asa channel formation region, the conductor 104 has a function as a gateelectrode, the insulator 112 a, the charge accumulation layer 112 b, andthe insulator 112 c each have a function as a gate insulator, theconductor 116 a has a function as a source electrode, and the conductor116 b has a function as a drain electrode. The insulator 106 a and theinsulator 106 c have functions of reducing the density of defect statesat the interfaces between the semiconductor 106 b and the insulator 106a and between the semiconductor 106 b and the insulator 106 c.Combination of materials used for the insulator 106 a, the semiconductor106 b, and the insulator 106 c will be described later. The conductor104, which serves as the gate electrode of the transistor Tr_1, iselectrically connected to a wiring WL_1. Note that the wiring WL_1 has afunction as a word line. Note that the transistor Tr_1 is not limited tothe structure illustrated in FIG. 1A. For example, some components suchas the insulators 106 a and 106 c are not necessarily provided.

The transistor Tr_1 includes the charge accumulation layer 112 b betweenthe conductor 104 and the semiconductor 106 b. Thus, the thresholdvoltage of the transistor Tr_1 corresponds to the polarity and amount ofcharge included in the charge accumulation layer 112 b. The thresholdvoltage of the transistor Tr_1 can be controlled by the chargeaccumulation layer 112 b; therefore, the transistor Tr_1 can serve as amemory cell (also referred to as a memory element) which stores datacorresponding to the threshold voltage.

As shown in the left of FIG. 2A, the threshold voltage of the transistorTr_1 is negative when electrons are not accumulated in the chargeaccumulation layer 112 b. When electrons are accumulated in the chargeaccumulation layer 112 b as shown in FIG. 2B, the threshold voltagechanges to cancel an electric field generated by the electrons, and thenthe threshold voltage becomes positive as shown in the right of FIG. 2A.That is, the transistor Tr_1 takes data “1” because it is on whenelectrons are not accumulated in the charge accumulation layer 112 b,and takes data “0” because of non-conduction when electrons areaccumulated in the charge accumulation layer 112 b. Although thedescription is about a two-valued memory cell here, a multivalued memorycell of three values or more (such as a four-valued, eight-valued,sixteen-valued, or thirty-two-valued memory cell) may be used. Note thatelectron injection into the charge accumulation layer 112 b will bedescribed later.

The transistors Tr_2 to Tr_2 n have the same structures as that of thetransistor Tr_1. Each of the gate electrodes of the transistors Tr_2 toTr_2 n is electrically connected to corresponding wirings WL_2 to WL_2n. The wirings WL_2 to WL_2 n each have a function as a word line.

As described above, the transistors Tr_1 to Tr_2 n each have a functionas a memory cell. The transistors Tr_1 to Tr_2 n are connected inseries; thus, they can be collectively called one memory cell string.Memory cell strings can be arranged in matrix over the substrate 100,for example. Each of the memory cell strings is electrically connectedto a selection transistor. Specifically, the memory cell strings arearranged over points of intersection of a plurality of straight linesextending in a first direction and a plurality of straight linesextending in a second direction over the substrate 100. The anglebetween the first direction and the second direction may be typically45° or 90°. However, the angle may be in the range of greater than orequal to 10° and less than or equal to 90°, greater than or equal to 30°and less than or equal to 90°, greater than or equal to 45° and lessthan or equal to 90°, or greater than or equal to 60° and less than orequal to 90°, for example. The arrangement of the memory cell strings ispreferably dense, and it depends on the shape of the memory cellstrings. A wiring SL and a wiring BL provided along the first direction,for example, can be shared between the memory cell strings formed alongthe first direction. Note that the arrangement of the memory cellstrings is not limited to a matrix arrangement. The wiring SL has afunction as a source line. The wiring BL has a function as a bit line.

The plurality of memory cell strings are collectively called a block.One block is supposed to include a×b memory cell strings, a is thenumber of memory cell strings in the first direction (a is a naturalnumber) and b is the number of memory cell strings in the seconddirection (b is a natural number). Note that the blocks may havedifferent numbers of memory cell strings. A rule of how to form theblocks may be determined as appropriate. In a block, the wiring BGL iselectrically connected to the conductor 132, for example. The conductors132 are electrically isolated from the wirings BGL between the blocks.In one block, wirings WL_1 to WL_2 n provided along the seconddirection, for example, can be shared between the memory cell stringsformed along the second direction. The wirings WL_1 to WL_2 n may beprovided for each of the blocks or may be shared between the blocksarranged along the second direction. Memory cells sharing the wiringsWL_1 to WL_2 n are collectively called a page. Note that the wirings BLand SL can be shared between blocks arranged along the first direction.

A source terminal of the transistor Tr_S1 is electrically connected tothe wiring SL, and its drain terminal of the transistor Tr_S1 iselectrically connected to a first terminal of the memory cell string. Adrain terminal of the transistor Tr_S2 is electrically connected to thewiring BL, and its source terminal of the transistor Tr_S2 iselectrically connected to a second terminal of the memory cell string.The transistors Tr_S1 and Tr_S2 can be called selection transistorsbecause the transistors control conduction or non-conduction between thememory cell string and the wirings.

The operations of writing and reading data to/from the semiconductordevice shown in FIGS. 1A and 1B will be described below.

<Reset Operation>

When data is written to each of the memory cells, data is preferablydeleted (data “1” is preferably written) in advance of the writingoperation. The operation of deleting data is also referred to as a resetoperation. The reset operation is performed in each block. For example,a reset operation can be performed in the following manner: a blockstoring data to be deleted is selected, an erasing potential V_(E)(e.g., 15 V) is applied to the wiring BGL electrically connected to theconductor 132, a low potential (a potential such as 0 V, at which thetransistors Tr_1 to Tr_2 n are turned off) is applied to the wiringsWL_1 to WL_2 n, and the transistors Tr_S1 and Tr_S2 are turned on asshown in FIG. 3A. Note that when the conductor 132 is not provided, areset operation can also be performed by an erasing potential V_(E)applied to the wirings SL and BL. Electrons stored in the chargeaccumulation layer 112 b of each of the transistors Tr_1 to Tr_2 n canbe extracted through the reset operation.

In a block from which data is not deleted, the electrical connectionbetween the conductor 132 and the wiring BGL is cut off so that anerasing potential V_(E) is not to be applied to the conductor 132.Alternatively, as shown in FIG. 3B, a potential such as an erasingpotential V_(E), at which the transistors Tr_1 to Tr_2 n are turned on,may be applied to the wirings WL_1 to WL_2 n electrically connected to ablock from which data is not deleted. That is, the charge accumulationlayer 112 b is not applied with a difference in potential which leadselectron extraction.

Note that data in a memory cell which is not subjected to rewriting ispreferably stored in a different region in advance of the resetoperation of the block.

<Writing Operation>

Next, a writing operation of data to each memory cell will be describedwith reference to FIGS. 4 to 6.

A writing operation of data can be performed for each of the abovepages. First, a writing potential (e.g., 15 V) is applied to a word lineof a page subjected to writing, and then a positive potential (apotential such as 3 V, at which a transistor is turned on) is applied toa word line of a page which is not subjected to writing. As shown inFIG. 4, a writing potential is applied to the wiring WL_1 first, andthen positive potentials are applied to the wirings WL_2 to WL_2 n. Inaddition, the transistor Tr_S1 electrically connected to the wiring SLis off, and the transistor Tr_S2 electrically connected to the wiring BLis on. Accordingly, a potential of the wiring BL is applied to thememory cell of the page subjected to writing. Data corresponding to thepotential of the wiring BL is written to the memory cell. Specifically,when a potential of the wiring BL is a low potential such as 0 V,electrons are injected into the charge accumulation layer 112 b becausea difference between the potential of the wiring BL and the writingpotential applied to the wiring WL_1 is increased. When the potential ofthe wiring BL is a positive potential, electrons are not injected intothe charge accumulation layer 112 b because a difference between thepotential of the wiring BL and the writing potential applied to thewiring WL_1 is decreased. That is, data “0” is written to the memorycell when a low potential is applied to the wiring BL, and the memorycell keeps data “1” when a positive potential is applied.

Data writing can be performed page by page in such a manner that each ofthe wirings BL is applied with a potential required in the correspondingmemory cell string. As shown in FIGS. 5 and 6, the same data writing isperformed also for the wirings WL_2 to WL_2 n, so that data writing canbe performed for the block or the whole of the semiconductor device.

Note that data other than the data “0” or data “1” can also be writtento the memory cell. For example, the amount of electrons injected intothe charge accumulation layer 112 b can be controlled on the basis of apotential of the wiring BL or the like or a potential applying period.

<Reading Operation>

Next, a reading operation of data written in each memory cell will bedescribed with reference to FIGS. 7 to 9.

A reading operation of data can also be performed for each of the pages.First, a low potential such as 0 V is applied to a word line of a pagesubjected to reading, and then a positive potential (a potential such as3 V, at which a transistor is turned on) is applied to a word line of apage which is not subjected to reading. As shown in FIG. 7, a lowpotential is applied to the wiring WL_1 first, and then positivepotentials are applied to the wirings WL_2 to WL_2 n. In addition, thetransistor Tr_S1 electrically connected to the wiring SL and thetransistor Tr_S2 electrically connected to the wiring BL are on. Areading potential such as 1 V is applied to the wiring BL, and a lowpotential such as 0 V is applied to the wiring SL. At this time, acurrent is supplied to the memory cell string if the memory cell hasdata “1,” and a current is not supplied to the memory cell string if thememory cell has data “0.” Accordingly, data of the memory cell can beread by detection of the current value at that time or by detection of apotential drop of the wiring BL.

Data in each of the memory cell strings is output to the wiring BL;thus, data per page can be read. As shown in FIGS. 8 and 9, the samedata reading is performed for the wirings WL_2 to WL_2 n, so that datareading subjected to the block or the whole of the semiconductor devicecan be performed.

As described above, the semiconductor device of one embodiment of thepresent invention has high integration due to the three-dimensionalarrangement of the memory cells. Thus, the semiconductor device has alarge storage capacity per footprint. For example, the semiconductordevice has a storage capacity of 1 Tbyte or more, 3 Tbyte or more, or 10Tbyte or more. The semiconductor device can also be called asemiconductor device including a nonvolatile or substantiallynonvolatile memory element because it can store data for a long period.

The semiconductor device of one embodiment of the present invention issuited for a storage device for computers because the semiconductordevice is capable of rewriting and storing data for a long period, andhas a large storage capacity. For example, the semiconductor device canbe used in a main storage device (also referred to as a main memory or amemory) that stores data inside a computer, an external storage device(also referred to as a storage or a second storage device) that storesdata outside a computer, or the like. Examples of the external storagedevice include a memory card and a solid state drive (SSD).

<Modification Example of Semiconductor Device>

The structure of the semiconductor device of one embodiment of thepresent invention is not limited to the structure in FIG. 1A. Forexample, the insulator 106 c may be provided to have a shape along theinsulator 130 with the semiconductor 106 b and the insulator 106 atherebetween as shown in FIG. 10. The insulator 112 a may be provided tohave a shape along the insulator 130 with the insulator 106 c, thesemiconductor 106 b, and the insulator 106 a therebetween. In addition,the charge accumulation layer 112 b may be provided to have a shapealong the insulator 130 with the insulator 112 a, the insulator 106 c,the semiconductor 106 b, and the insulator 106 a therebetween. Theconductors 116 a and 116 b in FIG. 1A can be omitted.

The transistors Tr_S1 and Tr_S2 may be FIN-type transistors as shown inFIG. 11.

<Components of Semiconductor Device>

The components of the semiconductor device will be described below.

The insulators 120, 122, 124, 126, 128, and 130 may each be formed tohave a single-layer structure or a stacked-layer structure including aninsulator containing, for example, boron, carbon, nitrogen, oxygen,fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon,gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium,or tantalum. For example, aluminum oxide, magnesium oxide, siliconoxide, silicon oxynitride, silicon nitride oxide, silicon nitride,gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide maybe used. Note that a “silicon oxynitride film” refers to a film thatincludes oxygen at a higher proportion than nitrogen, and a “siliconnitride oxide film” refers to a film that includes nitrogen at a higherproportion than oxygen.

Note that the insulators 120, 122, 124, 126, 128, and 130 have functionsof isolating adjacent elements, wirings, and the like in some cases;thus, an insulator with a low dielectric constant is preferably used.For example, an insulator with a dielectric constant of 5 or lower,preferably 4 or lower, or further preferably 3 or lower is used.Specifically, an insulator containing silicon and oxygen or an insulatorcontaining fluorine in addition to silicon and oxygen, or the like ispreferably used. At least one of the insulators 120, 122, 124, 126, 128,and 130 may be a space.

At least one of the insulators 120, 122, 124, 126, 128, and 130preferably contains an insulator having a function of blocking oxygenand impurities such as hydrogen (a function of not transmitting oxygenor impurities such as hydrogen). When an insulator that has a functionof blocking oxygen and impurities such as hydrogen is placed near thetransistors Tr_1 to Tr_2 n, the electrical characteristics of thetransistors Tr_1 to Tr_2 n can be stable.

When the transistors Tr_1 to Tr_2 n are transistors including an oxidesemiconductor, it is preferable that the adjacent insulator 130 or/andinsulator 126 be an insulator including excess oxygen. The excess oxygencan be used to reduce oxygen vacancy in the oxide semiconductor. Notethat excess oxygen means oxygen in an insulator or the like which doesnot bond with (which is liberated from) the insulator or the like or haslow bonding energy with the insulator or the like.

An insulator including excess oxygen may release oxygen, the amount ofwhich is higher than or equal to 1×10¹⁸ atoms/cm³, higher than or equalto 1×10¹⁹ atoms/cm³, or higher than or equal to 1×10²⁰ atoms/cm³(converted into the number of oxygen atoms) in thermal desorptionspectroscopy (TDS) analysis in the range of a surface temperature of100° C. to 700° C. inclusive or 100° C. to 500° C. inclusive.

The method for measuring the amount of released oxygen using TDSanalysis will be described below.

The total amount of gas released from a measurement sample in TDSanalysis is proportional to the integral value of the ion intensity ofthe released gas. Then, comparison with a reference sample is made,whereby the total amount of released gas can be calculated.

For example, the number of oxygen molecules (N_(O2)) released from ameasurement sample can be calculated according to the following formulausing the TDS results of a silicon substrate containing hydrogen at apredetermined density, which is a reference sample, and the TDS resultsof the measurement sample. Here, all gases having a mass-to-charge ratioof 32 which are obtained in the TDS analysis are assumed to originatefrom an oxygen molecule. Note that CH₃OH, which is a gas having themass-to-charge ratio of 32, is not taken into consideration because itis unlikely to be present. Furthermore, an oxygen molecule including anoxygen atom having a mass number of 17 or 18 which is an isotope of anoxygen atom is not taken into consideration either because theproportion of such a molecule in the natural world is negligible.

N _(O2) =N _(H2) /S _(H2) ×S _(O2)×α

The value N_(H2) is obtained by conversion of the number of hydrogenmolecules desorbed from the reference sample into densities. The valueS_(H2) is the integral value of ion intensity when the reference sampleis subjected to the TDS analysis. Here, the reference value of thereference sample is set to N_(H2)/S_(H2). The value S_(O2) is theintegral value of ion intensity when the measurement sample is analyzedby TDS. The value a is a coefficient affecting the ion intensity in theTDS analysis. Refer to Japanese Published Patent Application No.H6-275697 for details of the above formula. The amount of releasedoxygen was measured with a thermal desorption spectroscopy apparatusproduced by ESCO Ltd., EMD-WA1000S/W, using a silicon substratecontaining a certain amount of hydrogen atoms as the reference sample.

Furthermore, in the TDS analysis, oxygen is partly detected as an oxygenatom. The ratio between oxygen molecules and oxygen atoms can becalculated from the ionization rate of the oxygen molecules. Note that,since the above a includes the ionization rate of the oxygen molecules,the number of the released oxygen atoms can also be estimated throughthe measurement of the number of the released oxygen molecules.

Note that N_(O2) is the number of the released oxygen molecules. Thenumber of released oxygen in the case of being converted into oxygenatoms is twice the number of the released oxygen molecules.

Furthermore, an insulator from which oxygen is released by heattreatment may contain a peroxide radical. Specifically, the spin densityattributed to the peroxide radical is greater than or equal to 5×10¹⁷spins/cm³. Note that the insulator containing a peroxide radical mayhave an asymmetric signal with a g factor of approximately 2.01 inelectron spin resonance (ESR).

In the case where the transistors Tr_S1 and Tr_S2 are silicontransistors including single crystal silicon, polycrystalline silicon,or the like, excess oxygen might be a factor in degrading the electricalcharacteristics. Accordingly, the insulator 122 preferably includes aninsulator having a low oxygen-transmitting property so that the excessoxygen does not enter the transistors Tr_S1 or Tr_S2.

On the contrary, hydrogen can be used to terminate dangling bonds ofsilicon. Consequently, electrical characteristics of the transistorsTr_S1 and Tr_S2 can be improved. Note that hydrogen becomes a factor indegrading the electrical characteristics of the transistors Tr_1 to Tr_2n in some cases, so that the insulator 122 preferably includes aninsulator having a low hydrogen-transmitting property.

Because of its small atomic radius or the like, hydrogen is likely to bediffused in an insulator (i.e., the diffusion coefficient of hydrogen islarge). For example, a low-density insulator has a highhydrogen-transmitting property. In other words, a high-density insulatorhas a low hydrogen-transmitting property. The density of a low-densityinsulator is not always low throughout the insulator; an insulatorincluding a low-density part is also referred to as a low-densityinsulator. This is because the low-density part serves as a hydrogenpath. Although a density that allows hydrogen to be transmitted is notlimited, it is typically lower than 2.6 g/cm³. Examples of a low-densityinsulator include an inorganic insulator such as silicon oxide orsilicon oxynitride and an organic insulator such as polyester,polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate,or acrylic. Examples of a high-density insulator include magnesiumoxide, aluminum oxide, germanium oxide, gallium oxide, yttrium oxide,zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, andtantalum oxide. Note that a low-density insulator and a high-densityinsulator are not limited to these insulators. For example, theinsulators may contain one or more of boron, nitrogen, fluorine, neon,phosphorus, chlorine, and argon.

An insulator having crystal grain boundaries can have a highhydrogen-transmitting property. In other words, hydrogen is less likelyto be transmitted through an insulator having no grain boundaries or fewgrain boundaries. For example, a non-polycrystalline insulator (e.g., anamorphous insulator) has a lower hydrogen-transmitting property thanthat of a polycrystalline insulator.

An insulator having a high hydrogen-bonding energy has a lowhydrogen-transmitting property in some cases. For example, when aninsulator which forms a hydrogen compound by bonding with hydrogen hasbonding energy at which hydrogen is not released at temperatures infabrication and operation of a device, the insulator can be in thecategory of an insulator having a low hydrogen-transmitting property.For example, an insulator which forms a hydrogen compound at higher thanor equal to 200° C. and lower than or equal to 1000° C., higher than orequal to 300° C. and lower than or equal to 1000° C., or higher than orequal to 400° C. and lower than or equal to 1000° C. has a lowhydrogen-transmitting property in some cases. An insulator which forms ahydrogen compound and which releases hydrogen at higher than or equal to200° C. and lower than or equal to 1000° C., higher than or equal to300° C. and lower than or equal to 1000° C., or higher than or equal to400° C. and lower than or equal to 1000° C. has a lowhydrogen-transmitting property in some cases. An insulator which forms ahydrogen compound and which releases hydrogen at higher than or equal to20° C. and lower than or equal to 400° C., higher than or equal to 20°C. and lower than or equal to 300° C., or higher than or equal to 20° C.and lower than or equal to 200° C. has a high hydrogen-transmittingproperty in some cases. Hydrogen which is released easily and liberatedcan be referred to as excess hydrogen.

The charge accumulation layer 112 b may be formed to have a single-layerstructure or a stacked-layer structure including an insulatorcontaining, for example, boron, carbon, nitrogen, oxygen, fluorine,magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium,germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, ortantalum. For example, aluminum oxide, magnesium oxide, silicon oxide,silicon oxynitride, silicon nitride oxide, silicon nitride, galliumoxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide may be used.

The insulators 112 a and 112 c may each be formed to have a single-layerstructure or a stacked-layer structure including an insulatorcontaining, for example, boron, carbon, nitrogen, oxygen, fluorine,magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium,germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, ortantalum. For example, aluminum oxide, magnesium oxide, silicon oxide,silicon oxynitride, silicon nitride oxide, silicon nitride, galliumoxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide may be used.

The charge accumulation layer 112 b is provided between the insulators112 a and 112 c. The charge accumulation layer 112 b has a function ofaccumulating electrons. For example, an insulator including an electrontrap is suitable for the charge accumulation layer 112 b. The electrontrap can be formed by addition of impurities, application of damages, orthe like. The electron trap may be formed at an interface between thecharge accumulation layer 112 b and the insulator 112 a or at aninterface between the charge accumulation layer 112 b and the insulator112 c. In that case, junction of different kinds of materials ispreferably formed between the charge accumulation layer 112 b and theinsulator 112 a and between the charge accumulation layer 112 b and theinsulator 112 c. When the interface between the charge accumulationlayer 112 b and the insulator 112 a includes an electron trap, theinsulator 112 c is not necessarily provided in some cases.Alternatively, when the interface between the charge accumulation layer112 b and the insulator 112 c includes an electron trap, the insulator112 a is not necessarily provided in some cases. Note that electrons arepreferably less likely to move in the charge accumulation layer 112 bbecause the charge accumulation layer 112 b is shared with the adjacentmemory cells. Note that when the adjacent memory cells and the chargeaccumulation layer 112 b are separated, electrons can move in the chargeaccumulation layer 112 b. That is, the charge accumulation layer 112 bmay be a semiconductor or a conductor.

The insulators 112 a and 112 c each preferably have a thickness whichleads to electron tunneling by the gate voltage or the back gate voltageso that electrons are injected to the charge accumulation layer 112 b.Note that, in order to prevent electron leakage during a time when thememory cell stores data, the thickness is preferably such a thicknessthat electron tunneling does not occur when the gate voltage or the backgate voltage is not applied. Note that it is difficult to totallyeliminate electron tunneling; therefore, the insulators 112 a and 112 cmay have a thickness at which data can be stored and electron tunnelingdoes not occur. The thickness of the insulators 112 a and 112 c may begreater than or equal to 3 nm and less than or equal to 15 nm,preferably greater than or equal to 4 nm and less than or equal to 10nm. An insulator with a large energy gap is preferably used so thatelectron leakage is prevented. The energy gaps of the insulators 112 aand 112 c are, for example, larger than or equal to 6 eV and smallerthan or equal to 10 eV, preferably larger than or equal to 7 eV andsmaller than or equal to 10 eV, further preferably larger than or equalto 8 eV and smaller than or equal to 10 eV.

Specifically, silicon nitride, silicon nitride oxide, or hafnium oxidethat has high density of defect states is preferably used for the chargeaccumulation layer 112 b. Silicon oxide or silicon oxynitride ispreferably used for the insulators 112 a and 112 c.

The conductors 154, 140, 142, 144, 146, 148, 104, 116 a, 116 b, 132,134, 136, and 138 each may be formed to have a single-layer structure ora stacked-layer structure including a conductor containing one or morekinds of, for example, boron, nitrogen, oxygen, fluorine, silicon,phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel,copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium,silver, indium, tin, tantalum, and tungsten. An alloy or a compound ofthe above element may be used, for example, and a conductor containingaluminum, a conductor containing copper and titanium, a conductorcontaining copper and manganese, a conductor containing indium, tin, andoxygen, a conductor containing titanium and nitrogen, or the like may beused.

The insulator 106 a, the semiconductor 106 b, and the insulator 106 cwill be described below.

Placing the insulator 106 a under the semiconductor 106 b and placingthe insulator 106 c over the semiconductor 106 b can improve electricalcharacteristics of the transistor in some cases.

The insulator 106 a, the semiconductor 106 b, and the insulator 106 ceach preferably include a CAAC-OS.

The semiconductor 106 b is an oxide containing indium, for example. Thesemiconductor 106 b can have high carrier mobility (electron mobility)by containing indium, for example. The semiconductor 106 b preferablycontains an element M. The element M is preferably aluminum, gallium,yttrium, tin, or the like. Other elements which can be used as theelement M are boron, silicon, titanium, iron, nickel, germanium,zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum,tungsten, and the like. Note that two or more of the above elements maybe used in combination as the element M in some cases. The element M isan element having a high bonding energy with oxygen, for example. Theelement M is an element whose bonding energy with oxygen is higher thanthat of indium. The element M is an element that can increase the energygap of the oxide, for example. Furthermore, the semiconductor 106 bpreferably contains zinc. When containing zinc, the oxide is easilycrystallized in some cases.

Note that the semiconductor 106 b is not limited to the oxide containingindium. The semiconductor 106 b may be, for example, an oxide which doesnot contain indium and contains zinc, gallium, tin, or the like such asa zinc tin oxide or a gallium tin oxide.

The semiconductor 106 b is formed using, for example, an oxide with awide energy gap. For example, the energy gap of the semiconductor 106 bis greater than or equal to 2.5 eV and less than or equal to 4.2 eV,preferably greater than or equal to 2.8 eV and less than or equal to 3.8eV, further preferably greater than or equal to 3 eV and less than orequal to 3.5 eV.

The insulators 106 a and 106 c are each an oxide containing one or moreor two or more elements contained in the semiconductor 106 b other thanoxygen, for example. Since the insulators 106 a and 106 c each containone or more or two or more elements contained in the semiconductor 106 bother than oxygen, a defect state is less likely to be formed at theinterface between the insulator 106 a and the semiconductor 106 b andthe interface between the semiconductor 106 b and the insulator 106 c.

The insulator 106 a, the semiconductor 106 b, and the insulator 106 cpreferably contain at least indium. In the case of using an In-M-Znoxide as the insulator 106 a, when the total proportion of In and M isassumed to be 100 atomic %, the proportions of In and M are preferablyset to be less than 50 atomic % and greater than 50 atomic %,respectively, and further preferably less than 25 atomic % and greaterthan 75 atomic %, respectively. In the case of using an In-M-Zn oxide asthe semiconductor 106 b, when the total proportion of In and M isassumed to be 100 atomic %, the proportions of In and M are preferablyset to be greater than 25 atomic % and less than 75 atomic %,respectively, and further preferably greater than 34 atomic % and lessthan 66 atomic %, respectively. In the case of using an In-M-Zn oxide asthe insulator 106 c, when the total proportion of In and M is assumed tobe 100 atomic %, the proportions of In and M are preferably set to beless than 50 atomic % and greater than 50 atomic %, respectively, andfurther preferably less than 25 atomic % and greater than 75 atomic %,respectively. Note that the insulator 106 c may be an oxide that is ofthe same type as the oxide of the insulator 106 a. Note that theinsulator 106 a and/or the insulator 106 c do/does not necessarilycontain indium in some cases. For example, the insulator 106 a and/orthe insulator 106 c may be gallium oxide. Note that the atomic ratiobetween the elements contained in the insulator 106 a, the semiconductor106 b, and the insulator 106 c is not necessarily a simple integerratio.

As the semiconductor 106 b, an oxide having an electron affinity higherthan those of the insulators 106 a and 106 c is used. For example, asthe semiconductor 106 b, an oxide having an electron affinity higherthan those of the insulators 106 a and 106 c by 0.07 eV or higher and1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, andfurther preferably 0.15 eV or higher and 0.4 eV or lower is used. Notethat the electron affinity refers to an energy difference between thevacuum level and the bottom of the conduction band.

An indium gallium oxide has a low electron affinity and a highoxygen-blocking property. Therefore, the insulator 106 c preferablyincludes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)]is, for example, higher than or equal to 70%, preferably higher than orequal to 80%, further preferably higher than or equal to 90%.

At this time, when gate voltage is applied, a channel is formed in thesemiconductor 106 b whose electron affinity is the highest among theinsulator 106 a, the semiconductor 106 b, and the insulator 106 c.

Here, in some cases, there is a mixed region of the insulator 106 a andthe semiconductor 106 b between the insulator 106 a and thesemiconductor 106 b. Furthermore, in some cases, there is a mixed regionof the semiconductor 106 b and the insulator 106 c between thesemiconductor 106 b and the insulator 106 c. The mixed region has a lowdensity of defect states. For that reason, the stack including theinsulator 106 a, the semiconductor 106 b, and the insulator 106 c has aband structure where energy is changed continuously at each interfaceand in the vicinity of the interface (continuous junction) (see FIG.12). Note that boundaries of the insulator 106 a, the semiconductor 106b, and the insulator 106 c are not clear in some cases.

At this time, electrons move mainly in the semiconductor 106 b, butneither in the insulator 106 a nor in the insulator 106 c. Note that theinsulator 106 a and the insulator 106 c can exhibit a property of any ofa conductor, a semiconductor, and an insulator when existing alone. Whenthe transistor operates, they each, however, have a region where achannel is not formed. Specifically, a channel is formed only in aregion near the interface between the insulator 106 a and thesemiconductor 106 b and a region near the interface between theinsulator 106 c and the semiconductor 106 b, whereas a channel is notformed in the other region. Therefore, the insulator 106 a and theinsulator 106 c can be called insulators when the transistor operates,and are thus referred to as, not semiconductors or conductors, butinsulators in this specification. The insulator 106 a, the semiconductor106 b, and the insulator 106 c are separately called semiconductor orinsulator only because of the relative difference in physical property.Therefore, for example, an insulator that can be used as the insulator106 a or the insulator 106 c can be used as the semiconductor 106 b insome cases. As described above, when the density of defect states at theinterface between the insulator 106 a and the semiconductor 106 b andthe density of defect states at the interface between the semiconductor106 b and the insulator 106 c are decreased, electron movement in thesemiconductor 106 b is less likely to be inhibited and the on-statecurrent of the transistor can be increased.

As factors in inhibiting electron movement are decreased, the on-statecurrent of the transistor can be increased. For example, in the casewhere there is no factor in inhibiting electron movement, electrons areassumed to be moved efficiently. Electron movement is also inhibited,for example, in the case where physical unevenness in a channelformation region is large.

To increase the on-state current of the transistor, for example, rootmean square (RMS) roughness with a measurement area of 1 μm×1 μm of thetop or bottom surface of the semiconductor 106 b (a formation surface;here, the top surface of the insulator 106 a) is less than 1 nm,preferably less than 0.6 nm, further preferably less than 0.5 nm, stillfurther preferably less than 0.4 nm. The average surface roughness (alsoreferred to as Ra) with the measurement area of 1 μm×1 μm is less than 1nm, preferably less than 0.6 nm, further preferably less than 0.5 nm,still further preferably less than 0.4 nm. The maximum difference (alsoreferred to as P−V) with the measurement area of 1 μm×1 μm is less than10 nm, preferably less than 9 nm, further preferably less than 8 nm,still further preferably less than 7 nm. RMS roughness, Ra, and P−V canbe measured using, for example, a scanning probe microscope SPA-500manufactured by SII Nano Technology Inc.

Moreover, the thickness of the insulator 106 c is preferably as small aspossible to increase the on-state current of the transistor. Forexample, the insulator 106 c is formed to include a region having athickness of less than 10 nm, preferably less than or equal to 5 nm,further preferably less than or equal to 3 nm. Meanwhile, the insulator106 c has a function of blocking entry of elements other than oxygen(such as hydrogen and silicon) included in the adjacent insulator intothe semiconductor 106 b where a channel is formed. For this reason, itis preferable that the insulator 106 c have a certain thickness. Forexample, the insulator 106 c is formed to include a region having athickness of greater than or equal to 0.3 nm, preferably greater than orequal to 1 nm, further preferably greater than or equal to 2 nm. Theinsulator 106 c preferably has an oxygen blocking property to suppressoutward diffusion of oxygen released from the other insulators.

To improve reliability, the insulator 106 a is preferably thick and theinsulator 106 c is preferably thin. For example, the insulator 106 aincludes a region with a thickness of, for example, greater than orequal to 10 nm, preferably greater than or equal to 20 nm, furtherpreferably greater than or equal to 40 nm, still further preferablygreater than or equal to 60 nm. When the thickness of the insulator 106a is made large, a distance from an interface between the adjacentinsulator and the insulator 106 a to the semiconductor 106 b in which achannel is formed can be large. Since the productivity of thesemiconductor device might be decreased, the insulator 106 a has aregion with a thickness of, for example, less than or equal to 200 nm,preferably less than or equal to 120 nm, further preferably less than orequal to 80 nm.

For example, a region with a silicon concentration measured by secondaryion mass spectrometry (SIMS) of higher than or equal to 1×10¹⁶ atoms/cm³and lower than or equal to 1×10¹⁹ atoms/cm³, preferably higher than orequal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³,further preferably higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan or equal to 2×10¹⁸ atoms/cm³ is provided, for example, between thesemiconductor 106 b and the insulator 106 a. A region with a siliconconcentration measured by SIMS of higher than or equal to 1×10¹⁶atoms/cm³ and lower than or equal to 1×10¹⁹ atoms/cm³, preferably higherthan or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸atoms/cm³, further preferably higher than or equal to 1×10¹⁶ atoms/cm³and lower than or equal to 2×10¹⁸ atoms/cm³ is provided between thesemiconductor 106 b and the insulator 106 c.

The semiconductor 106 b includes a region with a hydrogen concentrationmeasured by SIMS of higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan or equal to 2×10²⁰ atoms/cm³, preferably higher than or equal to1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁹ atoms/cm³, furtherpreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 1×10¹⁹ atoms/cm³, and still further preferably higher than orequal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³.It is preferable to reduce the hydrogen concentration in the insulator106 a and the insulator 106 c in order to reduce the hydrogenconcentration in the semiconductor 106 b. The insulator 106 a and theinsulator 106 c each include a region with a hydrogen concentrationmeasured by SIMS of higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan or equal to 2×10²⁰ atoms/cm³, preferably higher than or equal to1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁹ atoms/cm³, furtherpreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 1×10¹⁹ atoms/cm³, and still further preferably higher than orequal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³.The semiconductor 106 b includes a region with a nitrogen concentrationmeasured by SIMS of higher than or equal to 1×10¹⁵ atoms/cm³ and lowerthan or equal to 5×10¹⁹ atoms/cm³, preferably higher than or equal to1×10¹⁵ atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³, furtherpreferably higher than or equal to 1×10¹⁵ atoms/cm³ and lower than orequal to 1×10¹⁸ atoms/cm³, and still further preferably higher than orequal to 1×10¹⁵ atoms/cm³ and lower than or equal to 5×10¹⁷ atoms/cm³.It is preferable to reduce the nitrogen concentration in the insulator106 a and the insulator 106 c in order to reduce the nitrogenconcentration in the semiconductor 106 b. The insulator 106 a and theinsulator 106 c each include a region with a nitrogen concentrationmeasured by SIMS of higher than or equal to 1×10¹⁵ atoms/cm³ and lowerthan or equal to 5×10¹⁹ atoms/cm³, preferably higher than or equal to1×10¹⁵ atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³, furtherpreferably higher than or equal to 1×10¹⁵ atoms/cm³ and lower than orequal to 1×10¹⁸ atoms/cm³, and still further preferably higher than orequal to 1×10¹⁵ atoms/cm³ and lower than or equal to 5×10¹⁷ atoms/cm³.

The above three-layer structure is an example. For example, a two-layerstructure including the semiconductor 106 b and the insulator 106 a orincluding the semiconductor 106 b and the insulator 106 c may beemployed. A four-layer structure in which any one of the semiconductorsdescribed as examples of the insulator 106 a, the semiconductor 106 b,and the insulator 106 c is provided under or over the insulator 106 a orunder or over the insulator 106 c may be employed. An n-layer structure(n is an integer of 5 or more) may be employed in which one of thesemiconductors described as examples of the insulator 106 a, thesemiconductor 106 b, and the insulator 106 c is provided at two or moreof the following positions: over the insulator 106 a, under theinsulator 106 a, over the insulator 106 c, and under the insulator 106c.

<Composition>

The composition of an In-M-Zn oxide will be described below. The elementM is aluminum, gallium, yttrium, tin, or the like. Other elements whichcan be used as the element M are boron, silicon, titanium, iron, nickel,germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium,tantalum, tungsten, and the like.

FIG. 13 is a triangular diagram whose vertices represent In, M, and Zn.In the diagram, [In] means the atomic concentration of In, [M] means theatomic concentration of the element M, and [Zn] means the atomicconcentration of Zn.

A crystal of an In-M-Zn oxide is known to have a homologous structureand is represented by InMO₃(ZnO)_(m) (m is a natural number). Since Inand M can be interchanged, the crystal can also be represented byIn_(1+α)M_(1−α)O₃(ZnO)_(m)(−1≦α≦1). This composition is represented byany of the dashed lines denoted as [In]:[M]:[Zn]=1+α:1−α:1,[In]:[M]:[Zn]=1+α:1−α:2, [In]:[M]:[Zn]=1+α:1−α:3,[In]:[M]:[Zn]=1+α:1−α:4, and [In]:[M]:[Zn]=1+α:1−α:5. Note that the boldlines on the dashed lines represent, for example, the compositions thateach allow oxides (raw materials) to be a solid solution when the oxidesare mixed and subjected to baking at 1350° C.

Thus, when an oxide has a composition close to the above compositionthat allows the oxide to be a solid solution, the crystallinity can beincreased. When an In-M-Zn oxide is deposited by a sputtering method,the composition of a target is different from the composition of thedeposited film in some cases. For example, using an In-M-Zn oxide inwhich an atomic ratio is 1:1:1, 1:1:1.2, 3:1:2, 4:2:4.1, 1:3:2, 1:3:4,or 1:4:5 as a target results in a film having an atomic ratio of 1:1:0.7(approximately 1:1:0.5 to 1:1:0.9), 1:1:0.9 (approximately 1:1:0.8 to1:1:1.1), 3:1:1.5 (approximately 3:1:1 to 3:1:1.8), 4:2:3 (approximately4:2:2.6 to 4:2:3.6), 1:3:1.5 (approximately 1:3:1 to 1:3:1.8), 1:3:3(approximately 1:3:2.5 to 1:3:3.5), or 1:4:4 (approximately 1:4:3.4 to1:4:4.4). Thus, in order to obtain a film with a desired composition, acomposition of a target may be selected in consideration of a change inthe composition.

<Structure of Oxide Semiconductor>

The structure of an oxide semiconductor will be described below.

An oxide semiconductor is classified into a single crystal oxidesemiconductor and the other, a non-single-crystal oxide semiconductor.Examples of a non-single-crystal oxide semiconductor include a c-axisaligned crystalline oxide semiconductor (CAAC-OS), a polycrystallineoxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), anamorphous-like oxide semiconductor (a-like OS), and an amorphous oxidesemiconductor.

From another perspective, an oxide semiconductor is classified into anamorphous oxide semiconductor and the other, a crystalline oxidesemiconductor. Examples of a crystalline oxide semiconductor include asingle crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxidesemiconductor, and an nc-OS.

An amorphous structure is generally thought to be isotropic and have nonon-uniform structure, to be metastable and not have fixed positions ofatoms, to have a flexible bond angle, and to have a short-range orderbut have no long-range order, for example.

In other words, a stable oxide semiconductor cannot be regarded as acompletely amorphous oxide semiconductor. Moreover, an oxidesemiconductor that is not isotropic (e.g., an oxide semiconductor thathas a periodic structure in a microscopic region) cannot be regarded asa completely amorphous oxide semiconductor. In contrast, an a-like OS,which is not isotropic, has an unstable structure that contains a void.Because of its instability, an a-like OS is close to an amorphous oxidesemiconductor in terms of physical properties.

<CAAC-OS>

First, a CAAC-OS will be described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axisaligned crystal parts (also referred to as pellets).

Analysis of a CAAC-OS by X-ray diffraction (XRD) will be described. Forexample, when the structure of a CAAC-OS including an InGaZnO₄ crystalthat is classified into the space group R−3m is analyzed by anout-of-plane method, a peak appears at a diffraction angle (2θ) ofaround 31° as shown in FIG. 14A. This peak is derived from the (009)plane of the InGaZnO₄ crystal, which indicates that crystals in theCAAC-OS have c-axis alignment, and that the c-axes are aligned in adirection substantially perpendicular to a surface over which theCAAC-OS film is formed (also referred to as a formation surface) or thetop surface of the CAAC-OS film. Note that a peak sometimes appears at a2θ of around 36° in addition to the peak at a 2θ of around 31°. The peakat a 2θ of around 36° is derived from a crystal structure classifiedinto the space group Fd−3m. Therefore, it is preferable that the CAAC-OSdo not show the peak.

On the other hand, in structural analysis of the CAAC-OS by an in-planemethod in which an X-ray is incident on the CAAC-OS in a directionparallel to the formation surface, a peak appears at a 2θ of around 56°.This peak is derived from the (110) plane of the InGaZnO₄ crystal. Whenanalysis (φ scan) is performed with 2θ fixed at around 56° and with thesample rotated using a normal vector to the sample surface as an axis (φaxis), as shown in FIG. 14B, a peak is not clearly observed. Incontrast, in the case where single crystal InGaZnO₄ is subjected to φscan with 2θ fixed at around 56°, as shown in FIG. 14C, six peaks whichare derived from crystal planes equivalent to the (110) plane areobserved. Accordingly, the structural analysis by XRD shows that thedirections of a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction will be described. Forexample, when an electron beam with a probe diameter of 300 nm isincident on a CAAC-OS including an InGaZnO₄ crystal in a directionparallel to the formation surface of the CAAC-OS, a diffraction pattern(also referred to as a selected-area electron diffraction pattern) shownin FIG. 14D can be obtained. In this diffraction pattern, spots derivedfrom the (009) plane of an InGaZnO₄ crystal are included. Thus, theelectron diffraction also indicates that pellets included in the CAAC-OShave c-axis alignment and that the c-axes are aligned in a directionsubstantially perpendicular to the formation surface or the top surfaceof the CAAC-OS. Meanwhile, FIG. 14E shows a diffraction pattern obtainedin such a manner that an electron beam with a probe diameter of 300 nmis incident on the same sample in a direction perpendicular to thesample surface. As shown in FIG. 14E, a ring-like diffraction pattern isobserved. Thus, the electron diffraction using an electron beam with aprobe diameter of 300 nm also indicates that the a-axes and b-axes ofthe pellets included in the CAAC-OS do not have regular orientation. Thefirst ring in FIG. 14E is considered to be derived from the (010) plane,the (100) plane, and the like of the InGaZnO₄ crystal. The second ringin FIG. 14E is considered to be derived from the (110) plane and thelike.

In a combined analysis image (also referred to as a high-resolution TEMimage) of a bright-field image and a diffraction pattern of a CAAC-OS,which is obtained using a transmission electron microscope (TEM), aplurality of pellets can be observed. However, even in thehigh-resolution TEM image, a boundary between pellets, that is, a grainboundary is not clearly observed in some cases. Thus, in the CAAC-OS, areduction in electron mobility due to the grain boundary is less likelyto occur.

FIG. 15A shows a high-resolution TEM image of a cross section of theCAAC-OS which is observed from a direction substantially parallel to thesample surface. The high-resolution TEM image is obtained with aspherical aberration corrector function. The high-resolution TEM imageobtained with a spherical aberration corrector function is particularlyreferred to as a Cs-corrected high-resolution TEM image. TheCs-corrected high-resolution TEM image can be observed with, forexample, an atomic resolution analytical electron microscope JEM-ARM200Fmanufactured by JEOL Ltd.

FIG. 15A shows pellets in which metal atoms are arranged in a layeredmanner. FIG. 15A proves that the size of a pellet is greater than orequal to 1 nm or greater than or equal to 3 nm. Therefore, the pelletcan also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OScan also be referred to as an oxide semiconductor including c-axisaligned nanocrystals (CANC). A pellet reflects unevenness of a formationsurface or a top surface of the CAAC-OS, and is parallel to theformation surface or the top surface of the CAAC-OS.

FIGS. 15B and 15C show Cs-corrected high-resolution TEM images of aplane of the CAAC-OS observed from the direction substantiallyperpendicular to the sample surface. FIGS. 15D and 15E are imagesobtained through image processing of FIGS. 15B and 15C. The method ofimage processing is as follows. The image in FIG. 15B is subjected tofast Fourier transform (FFT), so that an FFT image is obtained. Then,mask processing is performed such that a range of from 2.8 nm⁻¹ to 5.0nm⁻¹ from the origin in the obtained FFT image remains. After the maskprocessing, the FFT image is processed by inverse fast Fourier transform(IFFT) to obtain a processed image. The image obtained in this manner iscalled an FFT filtering image. The FFT filtering image is a Cs-correctedhigh-resolution TEM image from which a periodic component is extracted,and shows a lattice arrangement.

In FIG. 15D, a portion where a lattice arrangement is broken is shown bya dashed line. A region surrounded by the dashed line is one pellet. Theportion denoted with the dashed line is a junction of pellets. Thedashed line draws a hexagon, which means that the pellet has a hexagonalshape. Note that the shape of the pellet is not always a regular hexagonbut is a non-regular hexagon in many cases.

In FIG. 15E, a dotted line denotes a boundary between a region with aregular lattice arrangement and another region with a regular latticearrangement. A clear crystal grain boundary cannot be observed even inthe vicinity of the dotted line. When a lattice point in the vicinity ofthe dotted line is regarded as a center and surrounding lattice pointsare joined, a distorted hexagon, pentagon, and/or heptagon can beformed, for example. That is, a lattice arrangement is distorted so thatformation of a crystal grain boundary is inhibited. This is probablybecause the CAAC-OS can tolerate distortion owing to a low density ofthe atomic arrangement in an a-b plane direction, an interatomic bonddistance changed by substitution of a metal element, and the like.

As described above, the CAAC-OS has c-axis alignment, its pellets(nanocrystals) are connected in an a-b plane direction, and the crystalstructure has distortion. For this reason, the CAAC-OS can also bereferred to as an oxide semiconductor including a c-axis-aligneda-b-plane-anchored (CAA) crystal.

The CAAC-OS is an oxide semiconductor with high crystallinity. Entry ofimpurities, formation of defects, or the like might decrease thecrystallinity of an oxide semiconductor. This means that the CAAC-OS hassmall amounts of impurities and defects (e.g., oxygen vacancies).

Note that the impurity means an element other than the main componentsof the oxide semiconductor, such as hydrogen, carbon, silicon, or atransition metal element. For example, an element (specifically, siliconor the like) having higher strength of bonding to oxygen than a metalelement included in an oxide semiconductor extracts oxygen from theoxide semiconductor, which results in disorder of the atomic arrangementand reduced crystallinity of the oxide semiconductor. A heavy metal suchas iron or nickel, argon, carbon dioxide, or the like has a large atomicradius (or molecular radius), and thus disturbs the atomic arrangementof the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities ordefects might be changed by light, heat, or the like. Impuritiescontained in the oxide semiconductor might serve as carrier traps orcarrier generation sources, for example. For example, oxygen vacancy inthe oxide semiconductor might serve as a carrier trap or serve as acarrier generation source when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies isan oxide semiconductor with low carrier density (specifically, lowerthan 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferablylower than 1×10¹⁰/cm³, and is higher than or equal to 1×10⁻⁹/cm³). Suchan oxide semiconductor is referred to as a highly purified intrinsic orsubstantially highly purified intrinsic oxide semiconductor. A CAAC-OShas a low impurity concentration and a low density of defect states.Thus, the CAAC-OS can be referred to as an oxide semiconductor havingstable characteristics.

<nc-OS>

Next, an nc-OS will be described.

Analysis of an nc-OS by XRD will be described. When the structure of annc-OS is analyzed by an out-of-plane method, a peak indicatingorientation does not appear. That is, a crystal of an nc-OS does nothave orientation.

For example, when an electron beam with a probe diameter of 50 nm isincident on a 34-nm-thick region of thinned nc-OS including an InGaZnO₄crystal in a direction parallel to the formation surface, a ring-likediffraction pattern (a nanobeam electron diffraction pattern) shown inFIG. 16A is observed. FIG. 16B shows a diffraction pattern obtained whenan electron beam with a probe diameter of 1 nm is incident on the samesample. As shown in FIG. 16B, a plurality of spots are observed in aring-like region. In other words, ordering in an nc-OS is not observedwith an electron beam with a probe diameter of 50 nm but is observedwith an electron beam with a probe diameter of 1 nm.

Furthermore, an electron diffraction pattern in which spots are arrangedin an approximately hexagonal shape is observed in some cases as shownin FIG. 16C when an electron beam with a probe diameter of 1 nm isincident on a region with a thickness of less than 10 nm. This meansthat an nc-OS has a well-ordered region, i.e., a crystal, in the rangeof less than 10 nm in thickness. Note that an electron diffractionpattern having regularity is not observed in some regions becausecrystals are aligned in various directions.

FIG. 16D shows a Cs-corrected high-resolution TEM image of a crosssection of an nc-OS observed from the direction substantially parallelto the formation surface. In a high-resolution TEM image, an nc-OS has aregion in which a crystal part is observed, such as the part indicatedby additional lines in FIG. 16D, and a region in which a crystal part isnot clearly observed. In most cases, the size of a crystal part includedin the nc-OS is greater than or equal to 1 nm and less than or equal to10 nm, or specifically, greater than or equal to 1 nm and less than orequal to 3 nm. Note that an oxide semiconductor including a crystal partwhose size is greater than 10 nm and less than or equal to 100 nm issometimes referred to as a microcrystalline oxide semiconductor. In ahigh-resolution TEM image of the nc-OS film, for example, a grainboundary is not always found clearly. Note that there is a possibilitythat the origin of the nanocrystal is the same as that of a pellet in aCAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as apellet in the following description.

As described above, in the nc-OS, a microscopic region (for example, aregion with a size greater than or equal to 1 nm and less than or equalto 10 nm, in particular, a region with a size greater than or equal to 1nm and less than or equal to 3 nm) has a periodic atomic arrangement.There is no regularity of crystal orientation between different pelletsin the nc-OS. Thus, the orientation of the whole film is not observed.Accordingly, in some cases, the nc-OS cannot be distinguished from ana-like OS or an amorphous oxide semiconductor, depending on an analysismethod.

Since there is no regularity of crystal orientation between the pellets(nanocrystals), the nc-OS can also be referred to as an oxidesemiconductor including random aligned nanocrystals (RANC) or an oxidesemiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as comparedwith an amorphous oxide semiconductor. Therefore, the nc-OS is likely tohave a lower density of defect states than an a-like OS and an amorphousoxide semiconductor. Note that there is no regularity of crystalorientation between different pellets in the nc-OS. Therefore, the nc-OShas a higher density of defect states than the CAAC-OS.

<a-Like OS>

An a-like OS has a structure intermediate between those of the nc-OS andthe amorphous oxide semiconductor.

FIGS. 17A and 17B are high-resolution cross-sectional TEM images of ana-like OS. FIG. 17A is the high-resolution cross-sectional TEM image ofthe a-like OS at the start of the electron irradiation. FIG. 17B is thehigh-resolution cross-sectional TEM image of the a-like OS after theelectron (e−) irradiation at 4.3×10⁸ e⁻/nm². FIGS. 17A and 17B show thatstripe-like bright regions extending vertically are observed in thea-like OS from the start of the electron irradiation. It can be alsofound that the shape of the bright region changes after the electronirradiation. Note that the bright region is presumably a void or alow-density region.

The a-like OS has an unstable structure because it contains a void. Toverify that an a-like OS has an unstable structure as compared with aCAAC-OS and an nc-OS, a change in structure caused by electronirradiation will be described below.

An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each ofthe samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample isobtained. The high-resolution cross-sectional TEM images show that allthe samples have crystal parts.

It is known that a unit cell of an InGaZnO₄ crystal has a structure inwhich nine layers including three In—O layers and six Ga—Zn—O layers arestacked in the c-axis direction. Accordingly, the spacing between theseadjacent layers is equivalent to the lattice spacing (also referred toas d value) on the (009) plane. The value is calculated to be 0.29 nmfrom crystal structural analysis. Accordingly, a portion where thespacing between lattice fringes is greater than or equal to 0.28 nm andless than or equal to 0.30 nm is regarded as a crystal part of InGaZnO₄in the following description. Each of lattice fringes corresponds to thea-b plane of the InGaZnO₄ crystal.

FIG. 18 shows change in the average size of crystal parts (at 22 pointsto 30 points) in each sample. Note that the crystal part sizecorresponds to the length of the lattice fringe. FIG. 18 indicates thatthe size of the crystal part in the a-like OS increases with an increasein the cumulative electron dose in obtaining TEM images, for example. Asshown in FIG. 18, a crystal part of approximately 1.2 nm (also referredto as an initial nucleus) at the start of TEM observation grows to asize of approximately 1.9 nm at a cumulative electron (e−) dose of4.2×10⁸ e⁻/nm². In contrast, the crystal part size in the nc-OS and theCAAC-OS shows little change from the start of electron irradiation to acumulative electron dose of 4.2×10⁸ e⁻/nm². As shown in FIG. 18, thecrystal part sizes in an nc-OS and a CAAC-OS are approximately 1.3 nmand approximately 1.8 nm, respectively, regardless of the cumulativeelectron dose. For observation of electron beam irradiation and TEM, aHitachi H-9000NAR transmission electron microscope was used. Theconditions of electron beam irradiations were as follows: theaccelerating voltage was 300 kV; the current density was6.7×10⁵e⁻/(nm²×s); and the diameter of irradiation region was 230 nm.

In this manner, growth of the crystal part in the a-like OS is sometimesinduced by electron irradiation. In contrast, in the nc-OS and theCAAC-OS, growth of the crystal part is hardly induced by electronirradiation. Therefore, the a-like OS has an unstable structure ascompared with the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS becauseit contains a void. Specifically, the density of the a-like OS is higherthan or equal to 78.6% and lower than 92.3% of the density of the singlecrystal oxide semiconductor having the same composition. The density ofeach of the nc-OS and the CAAC-OS is higher than or equal to 92.3% andlower than 100% of the density of the single crystal oxide semiconductorhaving the same composition. Note that it is difficult to deposit anoxide semiconductor having a density of lower than 78% of the density ofthe single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomicratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, thedensity of the a-like OS is higher than or equal to 5.0 g/cm³ and lowerthan 5.9 g/cm³. For example, in the case of the oxide semiconductorhaving an atomic ratio of In:Ga:Zn=1:1:1, the density of each of thenc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lowerthan 6.3 g/cm³.

Note that in the case where an oxide semiconductor having a certaincomposition does not exist in a single crystal structure, single crystaloxide semiconductors with different compositions are combined at anadequate ratio, which makes it possible to calculate density equivalentto that of a single crystal oxide semiconductor with the desiredcomposition. The density of a single crystal oxide semiconductor havingthe desired composition can be calculated using a weighted averageaccording to the combination ratio of the single crystal oxidesemiconductors with different compositions. Note that it is preferableto use as few kinds of single crystal oxide semiconductors as possibleto calculate the density.

As described above, oxide semiconductors have various structures andvarious properties. Note that an oxide semiconductor may be a stackedlayer including two or more of an amorphous oxide semiconductor, ana-like OS, an nc-OS, and a CAAC-OS, for example.

This application is based on Japanese Patent Application serial No.2015-106145 filed with Japan Patent Office on May 26, 2015, the entirecontents of which are hereby incorporated by reference.

1. A semiconductor device comprising: a substrate; an insulator over thesubstrate; and a memory cell string comprising a plurality oftransistors connected in series, wherein the memory cell string isprovided on a side surface of the insulator, and wherein the pluralityof transistors each overlap with each other in a direction perpendicularto a top surface of the substrate.
 2. The semiconductor device accordingto claim 1, wherein the plurality of transistors each comprise a gateinsulator and a gate electrode, wherein the gate insulator comprises afirst insulator, a second insulator, and a charge accumulation layer,and wherein the charge accumulation layer is positioned between thefirst insulator and the second insulator.
 3. The semiconductor deviceaccording to claim 1, wherein the plurality of transistors each comprisean oxide semiconductor.
 4. The semiconductor device according to claim3, wherein the oxide semiconductor comprises indium, an element M(aluminum, gallium, yttrium, or tin), and zinc.
 5. The semiconductordevice according to claim 1 further comprising a first transistor and asecond transistor over the substrate, wherein a source terminal of thefirst transistor is electrically connected to a first terminal of thememory cell string, and wherein a drain terminal of the secondtransistor is electrically connected to a second terminal of the memorycell string.
 6. The semiconductor device according to claim 5, whereinthe first transistor and the second transistor each comprise singlecrystal silicon.
 7. The semiconductor device according to claim 5,wherein the first transistor and the second transistor each are betweenthe substrate and the insulator.
 8. A semiconductor device comprising: asubstrate; an insulator over the substrate; and a plurality of memorycell strings, the plurality of memory cell strings each comprise aplurality of transistors connected in series, wherein the plurality ofmemory cell strings each are provided on a side surface of theinsulator, and wherein the plurality of transistors of one memory cellstrings each overlap with each other in a direction perpendicular to atop surface of the substrate.
 9. The semiconductor device according toclaim 8, wherein the plurality of transistors each comprise a gateinsulator and a gate electrode, wherein the gate insulator comprises afirst insulator, a second insulator, and a charge accumulation layer,and wherein the charge accumulation layer is positioned between thefirst insulator and the second insulator.
 10. The semiconductor deviceaccording to claim 8, wherein the plurality of transistors each comprisean oxide semiconductor.
 11. The semiconductor device according to claim10, wherein the oxide semiconductor comprises indium, an element M(aluminum, gallium, yttrium, or tin), and zinc.
 12. The semiconductordevice according to claim 10 further comprising a first transistor and asecond transistor over the substrate, wherein a source terminal of thefirst transistor is electrically connected to a first terminal of eachof the plurality of memory cell strings, and wherein a drain terminal ofthe second transistor is electrically connected to a second terminal ofeach of the plurality of memory cell strings.
 13. The semiconductordevice according to claim 12, wherein the first transistor and thesecond transistor each comprise single crystal silicon.
 14. Thesemiconductor device according to claim 12, wherein the first transistorand the second transistor each are between the substrate and theinsulator.